DocumentCode :
628540
Title :
3D Power module with embedded WLCSP
Author :
Shichun Qu ; Jihwan Kim ; Marcus, G. ; Ring, Matthias
Author_Institution :
Fairchild Semicond., San Jose, CA, USA
fYear :
2013
fDate :
28-31 May 2013
Firstpage :
1230
Lastpage :
1234
Abstract :
The qualifications of a 2×3 and a 7×7 embedded WLCSP power module were shared in this paper. The 2×3 module was built on a switching voltage regulator with three passive components and one embedded WLCSP (2×3 at 0.4 mm pitch). The chip to module size ratio is 18.1 percent. The 7×7 module was built on a 7×7, 0.4 mm pitch WLCSP daisy chain test chip and five passive components. The silicon to module size ratio is 52.4 percent. Both 2×3 modules and 7×7 modules were subjected to drop test and temperature cycling test (TMCL). In addition, functional 2×3 modules underwent more device level reliability tests, such as dynamic optional life (DOPL), temperature humidity bias test (THBT), high temperature storage life (HTSL) and TMCL, etc. Solid chip to module, passives to module interconnect reliability was demonstrated alongside the robust module board level reliabilities. With adoption of PCB build up technology, the embedded WLCSP module offers 3D packaging options that are readily available to customers who demand full functionality in a small package and an attractive cost. Compared to other 3D packaging options, routing flexibility and robust interconnect reliability of the embedded module are distinguishing benefits. More designs taking advantages of this packaging technology are expected in the coming years.
Keywords :
chip scale packaging; integrated circuit interconnections; integrated circuit reliability; multichip modules; voltage regulators; wafer level packaging; 3D packaging options; 3D power module; DOPL; HTSL; PCB build up technology; THBT; TMCL; WLCSP daisy chain test chip; device level reliability tests; drop test; dynamic optional life; embedded WLCSP module; embedded WLCSP power module; embedded module; functional modules; high temperature storage life; module board level reliability; module interconnect reliability; one embedded WLCSP; packaging technology; passive components; robust interconnect reliability; routing flexibility; silicon to module size ratio; solid chip; switching voltage regulator; temperature cycling test; temperature humidity bias test; Copper; Packaging; Robustness; Silicon; Soldering; Substrates;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
Conference_Location :
Las Vegas, NV
ISSN :
0569-5503
Print_ISBN :
978-1-4799-0233-0
Type :
conf
DOI :
10.1109/ECTC.2013.6575732
Filename :
6575732
Link To Document :
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