DocumentCode :
628554
Title :
A lead-frame pre-mold coreless substrate development
Author :
Lan, Chang-Yi Albert ; Hsiao, C.S. ; Jensen Tsai ; Eason Chen ; Otis Hung
Author_Institution :
Siliconware Precision Ind. Co., Ltd., Taichung, Taiwan
fYear :
2013
fDate :
28-31 May 2013
Firstpage :
1336
Lastpage :
1340
Abstract :
It is well-known that thick substrate core has obviously increased package thickness and also weakened device performance, including electrical and thermal points of view. Therefore, as a NEW innovative coreless structure, a substrate with the features of lead-frame with pre-molding compound techniques has aroused lots of attention in IC semiconductor industry. It has brought not only thin package and device performance benefits, but also tremendous cost down benefits. Compared with traditional lead-frame types of packages (such as QFN, QFP, and so on) with NO trace, the above coreless substrate with trace routing capability can effectively shrink package size to save PCB board space and also shorten wire length to improve device electrical performance. Moreover, its BGA solder ball can enhance better SMT yield & Reliability performance as well, which compared with no solder ball in traditional QFN and QFP packages. However, without rigid substrate core material supporting, package warpage becomes a dominant issue for coreless substrate. It has slowed down or even inhibited sometimes for people to introduce it into production. Therefore, a lot of development works for package warpage improvement were intensively studied in these years, including mold compound raw material selection(which focus on its CTE and Tg adjustments), mold compound cure process temperature optimization, and lead-frame layout density and metal thickness definition, and so on. In the long run, as a ultra low cost solution under certain conditions, the above coreless substrate with multi-trace layer and finer pitch of plating trace capabilities can be easily applied to replace not only wire-bonding FBGA (Fine pitch Ball Grid Array) low-end products, but also FCCSP high-end products In this study, besides its benefits and challenges are introduced, a lot of mechanical stress simulation models and DOE studies are also addressed how to effectively reduce package warpage and then eventually im- rove its SMT yield and reliability performance.
Keywords :
ball grid arrays; integrated circuit design; integrated circuit packaging; integrated circuit reliability; substrates; surface mount technology; BGA solder ball; DOE studies; IC semiconductor industry; SMT yield; innovative coreless structure; lead-frame layout density; mechanical stress simulation models; metal thickness definition; mold compound cure process temperature optimization; mold compound raw material selection; multitrace layer; package warpage; pre-molding compound techniques; reliability performance; rigid substrate core material supporting; thick substrate core; trace routing capability; Assembly; Compounds; Flip-chip devices; Lead; Reliability; Substrates; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
Conference_Location :
Las Vegas, NV
ISSN :
0569-5503
Print_ISBN :
978-1-4799-0233-0
Type :
conf
DOI :
10.1109/ECTC.2013.6575746
Filename :
6575746
Link To Document :
بازگشت