Versatile Z-axis interconnection-based coreless technology solutions for next generation packaging

This paper discusses a novel strategy to combine Z-interconnect and coreless technology together to fabricate high density substrates for next generation packaging. The process starts with coreless fabrication of building blocks including signal and joining subcomposites (subs), and subsequently join and interconnect them by a lamination process. Through holes in the joining subs are filled with a conductive adhesive formulated using controlled-sized metallic particles to produce electrical connection between signal subs during lamination. A variety of filled joining and signal subs are fabricated to form a various combination of multilayer high density structures including rigid, rigid-rigid, rigid-flex, stacked packages, or RF substrates. Coreless z-axis interconnect flip-chip packages were evaluated at both the subcomposite and composite levels to understand and reduce paste-to-package CTE mismatch. As a case study, a coreless z-axis interconnect construction for a 150 μm pitch flip-chip package having mixed dielectric was used to evaluate CTE and warpage. The flip-chip package shows room temperature warpage averaged 56 microns, reducing to 45 microns near reflow temperature. S-parameter measurement was used to gauge electrical performance, and the coreless Z-interconnect package showed very low loss at multi-gigahertz frequencies. The current process can be used to fabricate a wide range of substrates with electrically conducting adhesive-based joints having diameters in the range of 55 to 500 μm.