DocumentCode :
628632
Title :
Fabrication of 3D-IC interposers
Author :
Keech, John ; Chaparala, Satish ; Shorey, Aric ; Piech, Garrett ; Pollard, Stephen
Author_Institution :
Corning Inc., Corning, NY, USA
fYear :
2013
fDate :
28-31 May 2013
Firstpage :
1829
Lastpage :
1833
Abstract :
Over the past several years, the semiconductor industry has seen some tremendous developments in using glass as an interposer substrate. Glass has many properties that make it an ideal substrate for interposer substrates such as: ultra-high resistivity, low dielectric constant, ultra-low electrical loss and adjustable coefficient of thermal expansion (CTE) that allows management of 3D-IC stacks. Regardless of technical performance, any glass based solution must also provide significant cost advantages in substrate material, via formation, and subsequent processing. Cost-Effective Solutions In this paper, we will cover how fusion formed glass provides cost-effective solutions for the manufacturing of interposer materials for as-formed 100 μm precision substrate with a pristine surface, without the need for polishing, thus eliminating the manufacturing steps for polishing and thinning. Design Considerations For effective implementation of glass substrates, processing costs for through-glass-vias (TGV) on ultra-thin glass is also a challenge. This paper will reference data from several different designs to demonstrate the impact of design on Corning´s TGV process cost relative to silicon solutions. It will also highlight processing lessons learned in fabricating TGV interposers from bare glass into complete packaged test vehicles and their impact on cost. Via Capabilities Furthermore, glasses via formation capabilities have dramatically improved over the past several months. Fully populated wafers with >100,000 through and blind holes (25 μm diameter) are fabricated today with 20μm diameters. We report on the significant enhancements demonstrated on important quality parameters. We will also report on strength parameters measured on TGV wafers and positive implications with respect to product reliability.
Keywords :
glass; integrated circuit manufacture; integrated circuit packaging; permittivity; polishing; semiconductor industry; thermal expansion; three-dimensional integrated circuits; vias; 3D-IC interposer fabrication; 3D-IC stacks; CTE; Corning´s TGV process cost; TGV interposers; TGV wafers; blind holes; coefficient of thermal expansion; cost-effective solutions; formation capability; fusion formed glass; glass based solution; glass substrates; interposer materials; interposer substrate; low dielectric constant; manufacturing steps; packaged test vehicles; polishing; precision substrate; pristine surface; processing costs; processing lessons; product reliability; quality parameters; semiconductor industry; silicon solutions; strength parameters; substrate material; thinning; through-glass-vias; ultra-high resistivity; ultra-low electrical loss; ultra-thin glass; Filling; Glass; Silicon; Substrates; Surface treatment; Vehicles;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
Conference_Location :
Las Vegas, NV
ISSN :
0569-5503
Print_ISBN :
978-1-4799-0233-0
Type :
conf
DOI :
10.1109/ECTC.2013.6575825
Filename :
6575825
Link To Document :
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