Novel design and reliability assessment of a 3D DRAM stacking based on Cu-Sn micro-bump bonding and TSV interconnection technology

In this paper, FEA model of Cu-Sn micro-bump bonding module and Cu-Sn micro-bump/BCB adhesive hybrid bonding module subjected to thermal cycling are built respectively. Two types of double-chip-stacking module, with and without BCB, are prepared. Followed by a thermal cycling test, during which mechanical and electrical test are also implemented to assess the reliability of the bonded micro-bumps. It is found that with the increase of cycle number or temperature gap, samples fabricated by pure micro-bump bonding, rather than micro-bump/adhesive hybrid bonding, demonstrate a better performance in reliability. Similar conclusion has been arrived from simulation results. Although BCB is beneficial in promoting chip level bonding strength, areas nearby micro-bumps become more risky. As a solution, a novel stacking scheme is designed to improve chip level bonding strength and avoid micro bump reliability loss at the same time. In this process, Cu-Sn micro-bump bonding, with special surface structure on chips instead of BCB adhesive, is adopted to enhance the chip bonding strength. And by this stacking scheme, multiple-chip-stacking module with single layer thinned to 50 microns are fabricated successfully. In reliability test, the stacked module performs well both in terms of chip level bonding strength and micro interconnect reliability. Finally, a 11-layer stacked chip module has been successfully fabricated.