Three dimensional interconnect using Au and pillar bumps

Fine pitch vertical interconnect has been extensively studied to meet the demand of next generation 3D packaging requirements. Copper pillar bump has received much of attentions as the choice for connecting chips due to its fine pitch and favorable reliability. Typical process involves copper pillar bump on one chip, CuNiAu, NiAu or Cu pad on the other chip, and interconnect is made through either a flux reflow process or an oxide removal process before bonding. While flux is difficult to clean, controlled atmosphere is required for oxide removal. Fine pitch copper pillar bump calls for less SnAg, intermetallic compound thus plays a greater role and joints become more brittle which tend to have early failure in temperature cycling test. In this paper, a fine pitch 3D chip stacking technology is proposed. Utilizing AuSn eutectic characteristic, one side of the joint is Au bumped and the other side is copper pillar bumped with SnAg on top of the copper. Both bumps were fabricated by readily available electroplating process. Bonding process is thermo-compression, performed under ambient atmosphere without the presence of flux. This bonding process is similar to the Chip-On-Film inner lead bonding process commonly used in the LCD driver IC industry. After the bonding process, selected underfill materials were applied to fill the gaps. Due to the presence of Au in the joint and its soft nature, C2C bonded structure filled with underfill without filler is capable of passing the temperature cycling test. Process parameters, material selections, joint formation and measurements, and reliability data are reported. Considerations for multiple stacks were studied. The reliability testing of the simulated 5-die stacked structure is ongoing at the time of publication.