DocumentCode
628657
Title
A lumped/discrete port de-embedding method by port connection error-cancelling network in full-wave electromagnetic modeling of 3D integration and packaging with vertical interconnects
Author
Zhaoqing Chen
Author_Institution
IBM Corp., Poughkeepsie, NY, USA
fYear
2013
fDate
28-31 May 2013
Firstpage
1980
Lastpage
1987
Abstract
In this paper, a lumped/discrete port de-embedding method by port connection error-cancelling network is proposed for full-wave modeling interconnect and packaging components with bump/pin array interfaces in 3D integration as well as conventional packaging systems. This method is based on the S-parameter matrix operation. Three calibration structures are simulated for extraction of the error-cancelling network. This error-cancelling network is inserted into the physical port connection interface in system SI simulation to cancel the port connection error caused by the port parasitic parameters and the uncertainty in port voltage and current definitions. Theoretically this method is a wide-band approach valid on every frequency point included in the S-parameter model. This approach is verified by two application examples with signal, power, and ground ports for power-aware SI applications including a 20-port 9-chip stack connected by TSV´s, a 20-port module-board-module structure, and the third example of a 36-signal-port printed circuit board via array for conventional SI applications. The connection error of cascaded physical networks after de-embedding by inserting the proposed error-cancelling network at the physical connection location is much smaller than the one without de-embedding.
Keywords
integrated circuit packaging; three-dimensional integrated circuits; 3D integration; S-parameter matrix operation; S-parameter model; TSV; calibration structures; connection interface; frequency point; full wave electromagnetic modeling; full wave modeling interconnect; lumped/discrete port de-embedding method; packaging components; packaging systems; port connection error cancelling network; port parasitic parameters; port voltage; printed circuit board; vertical interconnects; Arrays; Calibration; Electromagnetics; Mathematical model; Ports (Computers); Scattering parameters; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
Conference_Location
Las Vegas, NV
ISSN
0569-5503
Print_ISBN
978-1-4799-0233-0
Type
conf
DOI
10.1109/ECTC.2013.6575850
Filename
6575850
Link To Document