Title :
Fast signal integrity methodology for PCB pre-layout analysis and layout quality check
Author :
Hsu, John ; Su, Tao ; Yuan-Liang Li ; Hsiung, Edward ; Kai Xiao ; Xiaoning Ye ; Kai-Bin Wu
Author_Institution :
Intel Corp., Taipei, Taiwan
Abstract :
In this paper, a fast signal integrity methodology using pseudo eye is introduced to characterize printed circuit board (PCB) channels. The pseudo eye and pseudo ratio are proposed as performance indicators of the channel. This methodology can be applied to not only the solution space check during the pre-layout design phase but also layout quality check before PCB manufacture. For pre-layout analysis, the fast methodology can significantly reduce the required simulation resource and remove the complexity of chip behaviors with the equalization (EQ) function. Moreover, the PCB layout can be very efficiently checked and the potential routing issues can be quickly identified.
Keywords :
printed circuit layout; EQ function; PCB channels; PCB manufacture; PCB prelayout design analysis; equalization function; fast signal integrity methodology; layout quality check; printed circuit board channels; pseudo eye; Crosstalk; Dielectric losses; Finite impulse response filters; Layout; Measurement; Routing; Silicon;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4799-0233-0
DOI :
10.1109/ECTC.2013.6575855