High-speed packages with imperfect power and ground planes

In this paper, power-plane and ground-plane characterization on laminate packages and on wafer-level packages are carried out, and the electrical performance, in terms of loop-inductance, power-net isolation, signal-net cross-talk, from the two packaging technologies are compared. Measurement data on test structures is used to correlate the simulation approaches for signal traces with holes in their ground planes. Impacts from imperfect power and ground planes are thoroughly investigated using frequency-domain method. A DDR parallel bus of high-speed I/O, with imperfect power and ground planes made in eWLB package is simulated in time-domain for eye-diagram analysis. The simulation data indicates the end electrical-performance is adequate for the DDR memory bus application, although the eWLB package is implemented in less metal layers than other packaging solutions.