Author_Institution :
State Key Lab. for Digital Manuf. Equip. & Technol., Huazhong Univ. of Sci. & Technol., Wuhan, China
Abstract :
Due to its many advantages over traditional 3D packaging technology, through silicon via (TSVs) is being widely used. However, there are still a variety of obstacles hindering it from being developed rapidly. One of them is the huge thermal stress induced by big CTE mismatch between silicon and copper, which would even induce interfacial delamination. In this paper, thermal stress is evaluated first through FEA analysis and severe stress concentration (about 300MPa) is found at the corner of copper attached to SiO2 dielectric layer when TSV is under serious temperature drop. Then a polymer-filled TSV is introduced, in which the thin SiO2 dielectric layer is replaced by a thick polymer isolation layer, conformal copper plating is used to realize the connection and the remaining hole in the copper via is filled with polymer material, and the analytical results reveal that thermal stress can be greatly reduced. What´s more, driving forces of both cracks in polymer-filled and copper-filled TSV are calculated under negative thermal loads to investigate whether and how a crack propagates if it is initiated at interface between silicon and copper. Only negative thermal loads are considered because it is found that strain energy release rate of a crack in polymer-filled TSV is much lower, but for the entire propagation process, phase angle is bigger than that of copper-filled one especially when the crack is short, showing that delamination in polymer-filled TSV is relatively tougher to initiate and propagate. Therefore, polymer-filled TSV has a higher thermo-mechanical reliability than the traditional TSV with wholly copper filled one. Furthermore, the effects of some factors, like polymer diameter, aspect ratio and copper diameter, on delamination are analyzed. It indicates that strain energy release rate increases greatly with increase of copper diameter and aspect ratio, but decreases when diameter of filled polymer increases.
Keywords :
copper; cracks; delamination; finite element analysis; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; polymers; thermal stresses; three-dimensional integrated circuits; 3D interconnects; 3D packaging technology; CTE mismatch; FEA analysis; aspect ratio; conformal copper plating; copper diameter; copper-filled through silicon vias; crack propagation; driving forces; interfacial delamination; phase angle; polymer diameter; polymer material; polymer-filled TSV; silicon dioxide dielectric layer; strain energy release rate; stress concentration; thermal stress; thermomechanical reliability; thick-polymer isolation layer; Copper; Delamination; Polymers; Strain; Stress; Thermal stresses; Through-silicon vias;
