Numerical comparison of the thermal performance of 3D stacking and Si interposer based packaging concepts

Author

Oprins, Herman ; Vandevelde, B. ; Badaroglu, Mustafa ; Gonzalez, M. ; Van der Plas, G. ; Beyne, Eric

Author_Institution

IMEC, Leuven, Belgium

fYear

2013

fDate

28-31 May 2013

Firstpage

2183

Lastpage

2188

Abstract

In this paper, the thermal performance and the thermal die-to-die coupling are compared for the case of a 3D stacked configuration and a Si TSV-interposer by means of detailed thermal finite element simulations. The comparison is applied to packages with two components: 10×10mm² logic chip and a 2×10mm² temperature sensitive SerDes chip. A one-to-one comparison is made for package configurations without heat sink and for packages with integrated heat spreader and high performance heat sink.

Keywords

elemental semiconductors; finite element analysis; heat sinks; silicon; thermal management (packaging); three-dimensional integrated circuits; 3D stacked configuration; 3D stacking; Si; Si TSV-interposer; Si interposer based packaging; heat sink; heat spreader; logic chip; temperature sensitive SerDes chip; thermal die-to-die coupling; thermal finite element simulation; thermal performance; Couplings; Finite element analysis; Heat sinks; Heating; Silicon; Stacking; Thermal resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd

Conference_Location

Las Vegas, NV

ISSN

0569-5503

Print_ISBN

978-1-4799-0233-0

Type

conf

DOI

10.1109/ECTC.2013.6575884

Filename

6575884