3D Modeling of high count fine pitch flip chip assemblies

Flip chip technology is increasingly prevalent in electronics assembly (3D System in Package), and is mainly used at fine pitch in the manufacture of megapixels large focal plane detectors arrays. To verify the reliability of these assemblies numerical simulations appear as the less expensive method. However, as very large assemblies contain an array of more than one million solder bumps, the repetitive simulation of such structures in optimization processes is inconceivable. To circumvent this difficulty, a model based on a micromechanical description of the effective thermo-elastic properties of the interconnection layer of the flip chip assembly is proposed in this study. The interconnection layer composed of solder bumps embedded in epoxy was replaced by a homogeneous equivalent material and the manufacturing process of the assembly was simulated. The homogenization method allows estimating mean values of local stress and strain in each constituent of the interconnection layer. To deduce the more accurate stress and strain fields in these phases, a structural zoom technique has been applied. The results attest stress concentration at the interface between solder bumps and substrate/chip, in accordance with experimental observations showing cracks initiation at this place. In order to validate the relevance of the proposed modeling, at the level of the flip chip assembly, numerical results were compared with experimental measurements in terms of macroscopic warpage. In view of obtained results, the simulation tactic proposed seems to be an adequate approach for improvement of optoelectronic components.