DocumentCode :
628725
Title :
Study of low load and temperature, high heat-resistant solid-phase Sn-Ag bonding with formation of Ag3Sn intermetallic compound via nanoscale thin film control for wafer-level 3D-stacking for 3D LSI
Author :
Yoneta, Kiyoto ; Sato, Ryota ; Iwata, Yoshiyuki ; Atsumi, Koichiro ; Okamoto, K. ; Sato, Yuuki
Author_Institution :
Osaka Univ., Suita, Japan
fYear :
2013
fDate :
28-31 May 2013
Firstpage :
2381
Lastpage :
2384
Abstract :
Through-silicon via (TSV) technology for 3D-LSI is attracting much attention as a means of alleviating the miniaturization limits on advanced semiconductor devices. Despite a great deal of research, low load (<;1MPa), low temperature (<;200°C) and short time (<;5min) solid phase bonding with high heat resistance (>350°C) to prevent the damage of weak low-k dielectric material etc. has not been realized. In this work, we examine a new Sn-Ag thin film bonding system to replace Cu-Cu bonding. It is found that Ag/Sn/nano Ag-nano Ag/Sn/Ag thin film bonding systems (especially when the film thickness of the surface Ag is controlled to around 10nm) is a promising approach because 1) it enables low load (<;0.4MPa), low temperature (<;180°C) and short time (<;5min) bonding, and 2) the bonded interface has a high heat resistance (>400°C) and joint strength (>29MPa). We simulate the effects of the surface Ag from the viewpoint of energy stability at the nanoscale bonding level. It is found that it may be possible to realize an optimal solid phase bonding system for wafer-level 3D-stacking for 3D LSI which can satisfy a hierarchical temperature based bonding method that include TSV formation.
Keywords :
circuit stability; dielectric materials; large scale integration; silver alloys; thermal resistance; thin film circuits; three-dimensional integrated circuits; tin alloys; wafer bonding; 3D LSI; Ag3Sn; TSV; energy stability; heat-resistant solid-phase bonding; intermetallic compound; low-k dielectric material; nanoscale bonding level; nanoscale thin film control; semiconductor device; thin film bonding system; through-silicon via technology; wafer-level 3D-stacking; Bonding; Films; Heating; Silicon; Surface treatment; Through-silicon vias; Tin;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
Conference_Location :
Las Vegas, NV
ISSN :
0569-5503
Print_ISBN :
978-1-4799-0233-0
Type :
conf
DOI :
10.1109/ECTC.2013.6575918
Filename :
6575918
Link To Document :
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