Realization of gate performance using hybrid SET-CMOS pass transistor based logic gate

In present research areas of VLSI design & Microelectronics technology, Single Electron Transistor is in a place of attraction for the researchers due to, ultralow power dissipation, feature size in nanoscale and characteristics like Coulomb blockade, it may replace Field Effect Transistor (FET). SET is very much advantageous than CMOS in few points. And from some different points CMOS is much advantageous than SET. So it is observed that Combination of CMOS and SET, i.e. hybridization is very much effective in the Nanoscale and low power VLSI circuits. Our paper has given an idea to make elemental Hybrid SET-CMOS pass transistor logic circuit and implementation of logic OR gate. The circuit simulation is done in Tanner environment using TSPICE, BSIM4.6.1 and MIB model. All the values, used are the room temperature operable values.