Double gate vertical tunnel FET for hybrid CMOS-TFET based low standby power logic circuits

We investigate the deteriorating effect of source voltage on the performance of N-type vertical tunnel FETs. A non-zero source voltage may appear due to series connection of FETs. Theoretical analysis, backed with TCAD simulation, highlights the role of source voltage in undesired band bending and consequent change in various electrical parameters. We propose a double gate vertical tunnel FET structure as a solution to this problem. Such a structure nullifies any undesired bending in energy bands due to source voltage. Further, we utilize the proposed TFET to design hybrid CMOS-TFET based low standby power logic circuits; where the intrinsic properties of tunnel FET ensures the reduction of standby mode leakage current and supply voltage, while the modified tunnel FET enables the series connection of FETs. The proposed hybrid circuit utilizes minimum number of N-type tunnel FETs and hence minimizes the need for advanced and susceptible process steps associated with vertical tunnel FETs. Compared with conventional low standby power circuits, the hybrid combination shows four orders of reduction in sleep mode leakage current.