DocumentCode :
62882
Title :
Memory Persistency: Semantics for Byte-Addressable Nonvolatile Memory Technologies
Author :
Pelley, Steven ; Chen, Peter M. ; Wenisch, Thomas F.
Author_Institution :
Univ. of Michigan, Ann Arbor, MI, USA
Volume :
35
Issue :
3
fYear :
2015
fDate :
May-June 2015
Firstpage :
125
Lastpage :
131
Abstract :
Emerging nonvolatile memory technologies (NVRAM) promise the performance of DRAM with the persistence of disk. However, constraining the NVRAM write order, necessary to ensure recovery correctness, limits the NVRAM write concurrency and degrades throughput. New memory interfaces are required to efficiently describe write constraints and allow high-performance and high-concurrency data structures. The authors introduce memory persistency, a new approach to designing persistent memory interfaces that builds on the familiar framework of memory consistency to provide an interface for constraining the order in which persistent writes can occur with respect to failure. Similar to memory consistency, memory persistency models may be relaxed to improve performance. The authors describe the design space of memory persistency, introduce several memory persistency models, and evaluate their ability to expose NVRAM write concurrency. Their results show that relaxed persistency models can accelerate system throughput 30 times by reducing NVRAM write constraints.
Keywords :
random-access storage; DRAM; NVRAM write concurrency; NVRAM write constraint; NVRAM write order; byte-addressable nonvolatile memory technology; memory persistency; persistent memory interface; Concurrent computing; Data structures; Instruction sets; Memory management; Nonvolatile memory; Programming; Random access memory; NVRAM; memory persistency; persistent memory;
fLanguage :
English
Journal_Title :
Micro, IEEE
Publisher :
ieee
ISSN :
0272-1732
Type :
jour
DOI :
10.1109/MM.2015.46
Filename :
7106393
Link To Document :
بازگشت