Optimized power performance and simulation of reversible logic multiplexer

The Reversible logic has emerged as more compatible and appropriate logic approaches and more prominent technology having its applications in the reversible operation based Low Power CMOS, Quantum Computing, Garbage inputs/outputs, Cryptography, Communication, nanotechnology, Optical Computing and Computer graphics. The Reversible logic circuit is very concise approach for the design of low power; low loss of information of computational structures that are very essential with the construction of arithmetic circuits used low power digital. This paper presents two new optimized reversible logic based gates circuits is one of the best design ability to this reversible half adder and half subtract or. The results with to the proposed design show that the circuits are more optimized in terms of delay, power supply (0.7V) and frequency. In this paper using design adder to 2:1 multiplexer and 3-transistor XOR gate. The power dissipation, power-delay and propagation delay produced using the new design are analyzed and compared with those of other design simulations. The results show that the proposed Reversible gate has ability to design both lower power consumption and a lower Power-Delay Product (PDP) value for PRT-l (1.912×10^-19 joule), frequency response 50.6 MHz´, duty cycle (44.29 %) periodic jitter (40.0 ns), frequency jitter (1.214 ns) and PRT-2 (5.160×10^-19 joule) frequency response 50.0 MHz´s, duty cycle (44.29 %). The transistor implementation of the proposed gates is done by using Virtuoso tool of cadence. Based on simulation results and analysis at 45 nm technology, some of the trade-offs are made in the design to improve the efficiency.