Scalable 3D-FPGA using wafer-to-wafer TSV interconnect of 15 Tbps/W, 3.3 Tbps/mm2

A “scalable 3D-FPGA” using TSV interconnects is proposed. This FPGA was designed on the basis of homogeneous 3D-stacking to extend the logic scale in proportion to the number of stacked layers. To improve Z-axis transmission performance, a wafer-to-wafer stacking process for lowering the capacitance of TSV was developed. An “embedded TSV“ design for the shorter on-chip wirings was also devised. Moreover, to reduce the clock skew between the stacked layers arising from global process variations, a 3D clock-synchronization scheme using a reference clock via TSVs was developed. To check connectivity between layers and improves its reliability, test and redundant circuits were embedded into the FPGA. We present the first demonstration of two stacked FPGA layers by using wafer-to-wafer via-last Cu-TSV process. Z-axis transmission performance was the highest, namely, 15 Tbps/W and 3.3 Tbps/mm². The clock skew between two layers was reduced by 60% using the new clock scheme.