DocumentCode
629115
Title
A 1.5nsec/2.1nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories
Author
Ohsawa, Takashi ; Miura, Shun ; Kinoshita, Keizo ; Honjo, Hiroaki ; Ikeda, Shoji ; Hanyu, Takahiro ; Ohno, Hideo ; Endoh, Tetsuo
Author_Institution
Center for Spintronics Integrated Syst., Tohoku Univ., Sendai, Japan
fYear
2013
fDate
11-13 June 2013
Abstract
A 1Mb STT-RAM with a 6T2MTJ cell is designed and fabricated using 90nm CMOS/MTJ process that can operate in 1.5nsec/2.1nsec random read/write cycle by adopting a background write scheme. It works around the problem of high error rate of MTJ switching in a short period of time at moderate drive current. The RAM is fast enough to be applicable to embedded memories such as L3 cache.
Keywords
CMOS memory circuits; cache storage; random-access storage; 6T2MTJ cell; CMOS/MTJ process; L3 cache; MTJ switching; STT-RAM; background write; memory size 1 MByte; nonvolatile e-memories; size 90 nm; time 1.5 ns; time 2.1 ns; CMOS integrated circuits; Computer architecture; Latches; Microprocessors; Random access memory; Switches; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology (VLSIT), 2013 Symposium on
Conference_Location
Kyoto
ISSN
0743-1562
Print_ISBN
978-1-4673-5226-0
Type
conf
Filename
6576613
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