Title :
A 3.6GB/s 1.3mW 400mV 0.051mm2 near-threshold voltage resilient router in 22nm tri-gate CMOS
Author :
Paul, Sudipta ; Abbott, Malcolm ; Kishinevsky, Eugene ; Aseron, Paolo ; Vangal, Sriram ; De, Vivek ; Taylor, Gareth
Author_Institution :
SoC Design Lab., Intel Corp., Hillsboro, OR, USA
Abstract :
A 6-port, 2-lane packet-switched input-buffered wormhole router forms the key building block of a 2×2 2D mesh network-on-chip (NoC). The router operates across a wide frequency (voltage) range of 1GHz (0.85V) to 67MHz (340mV), dissipating 28.5mW to 675μW and achieves 3.3X improvement in energy-efficiency at an optimum supply voltage (VOPT) of 400mV. The resilient router incorporates an end-to-end forward error correction code (ECC) and withinrouter recovery from transient timing failures using error-detection sequentials and a FLIT replay scheme, to achieve 28% (at 0.7V) to 63% (at VOPT) higher bandwidths.
Keywords :
CMOS integrated circuits; forward error correction; logic design; network routing; network-on-chip; 2D mesh network-on-chip; 6-port 2-lane packet-switched input-buffered wormhole router; FLIT replay scheme; bit rate 3.6 Gbit/s; end-to-end forward error correction code; energy-efficiency; error-detection sequentials; frequency 1 GHz to 67 MHz; near-threshold voltage resilient router; optimum supply voltage; power 1.3 mW; power 28.5 mW to 675 muW; size 22 nm; transient timing failures; tri-gate CMOS; voltage 0.7 V; voltage 0.85 V to 340 mV; voltage 400 mV; wide frequency voltage range; Bandwidth; CMOS integrated circuits; Error correction codes; Forward error correction; Synchronization; Temperature measurement;
Conference_Titel :
VLSI Technology (VLSIT), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5226-0
