System scaling and collaborative open innovation

Giga trends in mobile computing, converged devices, cloud, and many other emerging applications continue to drive the growth of Si-based nano-electronics industry. A holistic approach must be taken to meet the demanding system requirements such as energy efficiency, integration density, information throughput, specialty features, and form factor. A new scaling paradigm is proposed, i.e., system scaling, by combining silicon wafer-based chip scaling and copper Through-Si-Via (TSV) 3D chip stacking to provide the ultimate energy-efficient scaling for system integration. Technically, chip scaling (Moore´s Law) can be extended to provide high-density and energy-efficient transistors and Cu/low-k on-chip interconnect operated at low supply voltages for the increasing use of multiple processor cores and parallelism. In addition, Cu-TSV 3D chip stacking provides a new system integration platform to heterogeneously integrate CMOS processors, memories, and specialty functions such as sensors, actuators, and other user interfaces. It enables better system partitioning for each system component to be optimized and integrated closely together for additional power saving, higher performance, equivalent density scaling, and form factor reduction. Many challenges are ahead and there are tremendous opportunities for industry-wide collaborative open innovation in this new era of system scaling to enable the continued growth of Si-based nano-electronic industry.