Effects of layout and process parameters on device/circuit performance and variability for 10nm node FinFET technology

We studied device and circuit performance and their variability for various design and process parameters using TCAD and an analytical RC model. At the 10nm technology node, σC_para and στ_pd became greater while σR_para and σI_on diminish due to lower ρ_c. L_g, H_fin, P_f2f, and P_p2p were found to be key parameters for mitigating variability. Increasing H_fin provides a path for further performance and area scaling with similar variability. And achieving lower ρ_c is the biggest module process challenge.