Logic fault detection and correction in SRAM based memory applications

SRAM memory cell is considered to be more suitable for designing memory, particularly, cache memory. A reliable memory system that can tolerate multiple transient errors in the memory words as well as transient errors in the encoder and decoder (corrector) circuitry is to be introduced. Such novel development is the fault-secure detector (FSD), its error-correcting code (ECC) definition and associated circuitry that can detect errors in the received encoded codeword despite experiencing multiple transient faults in its circuitry. Majority logic decodable codes are suitable for most of the memory applications due to their capability of correcting a large number of errors. However, they require a large decoding time that impacts memory performance. The proposed fault-detection method significantly reduces memory access time when there is no error in the data read. Further, the occurrence of fault may reduced by proper designing of SRAM cells, care should be taken in precharging, data read and write, particularly, by providing read stability as well as write ability.