Design and performance analysis of reversible logic multiplexer using nanoscale technology

Reversible logic has emerged as one of the most important approaches and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Garbage inputs/outputs, Cryptography, Communication, nanotechnology, Optical Computing and Computer graphics. This paper presents a novel reversible multiplexer gate is proposed and the design of differential reversible multiplexer using the proposed reversible gate is discussed. The results of the proposed design show that the circuits are more optimized in terms of delay, power supply (0.7V) and voltage gain (0.76V). The power dissipation, power-delay and propagation delay produced using the new design are analyzed and compared with those of other design simulations. The results show that the proposed Reversible multiplexer has both lower power consumption and a lower Power-Delay Product (PDP) value (2.384 ×10^-25 joule), frequency response 50.0 MHz´s. The transistor implementation of the proposed gates is done by using Virtuoso tool of cadence. Based on simulation results and analysis at 45 nm technology, some of the trade-offs are made in the design to improve the efficiency.