Design and implementation of FPGA based high resolution digital pulse width modulator

Author

Sabarinath, V. ; Sivanandam, K.

Author_Institution

K.S. Rangasamy Coll. of Technol., Tiruchengode, India

fYear

2013

fDate

3-5 April 2013

Firstpage

410

Lastpage

414

Abstract

Advantages and recent developments of digital control have led to an increasing use of digital pulse width modulators. The resolution of the digital pulse width modulator determines the accuracy in the output current/voltage. So resolution has direct influence in the performance of the system. This paper presents three architectures to improve the resolution of the digital pulse width modulator. Among these two architectures are based on the DCM (Digital Clock Manager) block and the other one is based on the IODELAYE1(I/O Delay Element) available in the VIRTEX-6 FPGA. These architectures are designed, implemented and compared to analyze the performance.

Keywords

clocks; digital control; field programmable gate arrays; modulators; pulse width modulation; DCM; I/O delay element; IODELAYE1; VIRTEX-6 FPGA; design; digital clock manager; digital control; high resolution digital pulse width modulator; output current/voltage; Clocks; Delays; Field programmable gate arrays; Pulse width modulation; Radiation detectors; Synchronization; Digital clock manager; Field programmable gate array(FPGA); IODELAYE1; pulse width modulator;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Signal Processing (ICCSP), 2013 International Conference on

Conference_Location

Melmaruvathur

Print_ISBN

978-1-4673-4865-2

Type

conf

DOI

10.1109/iccsp.2013.6577085

Filename

6577085