Design and implementation of FPGA based high resolution digital pulse width modulator

Advantages and recent developments of digital control have led to an increasing use of digital pulse width modulators. The resolution of the digital pulse width modulator determines the accuracy in the output current/voltage. So resolution has direct influence in the performance of the system. This paper presents three architectures to improve the resolution of the digital pulse width modulator. Among these two architectures are based on the DCM (Digital Clock Manager) block and the other one is based on the IODELAYE1(I/O Delay Element) available in the VIRTEX-6 FPGA. These architectures are designed, implemented and compared to analyze the performance.