A novel flip-flop design for low power clocking system

Author

Noble, G. ; Sakthivel, S.M.

Author_Institution

Sch. of Electron. Eng. (SENSE), VIT Univ., Chennai, India

fYear

2013

fDate

3-5 April 2013

Firstpage

627

Lastpage

631

Abstract

Dual edge triggering is an effective method for reducing the power consumption in the clock distribution network. This paper compares two existing design of flip-flop CDMFF and CPSFF with the proposed design of the dual edge triggered flip-flop (DE-CPSFF). The design eliminates the redundant transitions of internal nodes when current data is same as the previous one using conditional technique. This will significantly reduces the power dissipation. Various TSPICE simulation with different input sequences is done. The design has been simulated using Tanner 13.0 EDA tool with 0.25 μm technology.

Keywords

SPICE; circuit simulation; clock distribution networks; flip-flops; logic design; power consumption; trigger circuits; DE-CPSFF; TSPICE simulation; Tanner 13.0 EDA tool; clock distribution network; conditional technique; current data; dual edge triggered flip-flop design; dual edge triggering; flip-flop CDMFF; input sequences; internal nodes; low power clocking system; power consumption; power dissipation; redundant transitions; Clocks; Flip-flops; Power demand; Power dissipation; Switches; Transistors; Very large scale integration; Flip-flop Low Power Clocking System; Sequential Elements Dual edge triggering;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Signal Processing (ICCSP), 2013 International Conference on

Conference_Location

Melmaruvathur

Print_ISBN

978-1-4673-4865-2

Type

conf

DOI

10.1109/iccsp.2013.6577130

Filename

6577130