Ultra-low voltage and high speed NP domino carry propagation chain

Author

Mahmood, Suhair M. ; Berg, Yngvar

Author_Institution

Dept. of Inf., Univ. of Oslo, Oslo, Norway

fYear

2013

fDate

20-21 June 2013

Firstpage

1

Lastpage

4

Abstract

In this paper, an Ultra Low Voltage NP domino logic style is presented to perform a 32 bit computation in a carry propagation chain. The presented logic style is targeted to operate at the supply voltages near the sub-threshold regime. Simulated results of 32-bit proposed carry chain compared to the conventional carry chain conclude that the proposed approach offers a superb improvement in terms of speed and EDP. The proposed carry chain has a relative delay and EDP of only 2.68% and 8% respectively compared to the conventional carry chain. The 32-bit ULV NP domino carry chain using 90nm TSMC CMOS process technology with a supply voltage of 300mV could be operated at a clock frequency of 50MHz.

Keywords

CMOS logic circuits; carry logic; high-speed integrated circuits; logic design; TSMC CMOS process technology; clock frequency; frequency 50 MHz; high speed NP domino carry propagation chain; size 90 nm; sub-threshold regime; supply voltages; ultra low voltage NP domino logic style; voltage 300 mV; word length 32 bit; Adders; CMOS integrated circuits; Delays; Inverters; Logic gates; Low voltage; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Faible Tension Faible Consommation (FTFC), 2013 IEEE

Conference_Location

Paris

Print_ISBN

978-1-4673-6105-7

Type

conf

DOI

10.1109/FTFC.2013.6577759

Filename

6577759