Towards reconfigurable processors for power-proportional computing

Today we witness a major shift in microelectronics engineering priorities. The cost of computation is no longer dominated by the cost of building computation hardware. Almost every consumer electronic device nowadays contains a powerful processor with one or, increasingly often, multiple computation cores that are cheap to manufacture. Growing demand for high-definition content and associated processing capabilities revealed the true cost of computation - energy. `Big data´ companies face large electricity bills; in other applications, such as healthcare and infrastructure monitoring, the energy constraint has a different form: instead of a large bill, one faces limited energy availability and has to resort to such measures as energy-harvesting. In both cases it is essential for the computation system to be adaptable to the inflow of energy and computation load which often vary dramatically during runtime. In this paper we discuss an approach to building processors with reconfigurable computation pipeline capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to model the microarchitecture of such a processor, discuss implementation details, and present preliminary experimental results on an example of Intel 8051 microcontroller.