DocumentCode
630000
Title
A 28nm ROM with Two-Step Decoding scheme and OD-space-effect minimization to achieve 30% speed and 190mV Vmin improvement
Author
Ching-Wei Wu ; Kuang-Ting Chen ; Lee, Razak ; Wei-Shuo Kao ; Hong-Jen Liao ; Chang, Joana ; Natarajan, Sriraam
Author_Institution
Memory Develop Project (MDP), Semicond. Manuf. Co. (TSMC), Hsinchu, Taiwan
fYear
2013
fDate
12-14 June 2013
Abstract
An OSE-less [Oxide-definition Space Effect less] twin bits ROM cell is proposed. A reduced layout proximity dependence effect in ROM array is proposed using an OSE-less twin bits ROM cell. A Two-Step Decoding circuitry scheme suitable for either single-end or differential sensing is invented to read out twin bits ROM data. This work improves access time by 30% and reduces Vccmin by 190mV with TSMC 28nm Low Power process.
Keywords
decoding; integrated circuit layout; read-only storage; OD space effect minimization; layout proximity dependence effect; low power process; oxide definition space effect; size 28 nm; twin bits ROM cell; two-step decoding circuit; Computer architecture; Decoding; Discharges (electric); Layout; Microprocessors; Read only memory; Sensors;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location
Kyoto
Print_ISBN
978-1-4673-5531-5
Type
conf
Filename
6578665
Link To Document