Title :
A 400MHz – 1.6GHz fast lock, jitter filtering ADDLL based burst mode memory interface
Author :
Hossain, M. ; Aquil, Farrukh ; Pak Chau ; Tsang, Brian ; Phuong Le ; Wei, Jason ; Stone, T. ; Daly, Barry ; Tran Chanh ; Eble, John ; Knorpp, Kurt ; Zerbe, Jared
Author_Institution :
Rambus Inc., Sunnyvale, CA, USA
Abstract :
A fast lock DLL based 800Mb/s to 3.2 Gb/s burst mode memory interface is implemented. The DLL employs a two-step TDC during power up from 0mW to lock within 3 cycles with residual error <; 33 mUI. Following initial lock, the DLL operates closed-loop to compensate for V,T drift consuming 6mW @ 1.6GHz. In addition the DLL filters high frequency input jitter and corrects 20% DCD without additional correction.
Keywords :
delay lock loops; integrated memory circuits; jitter; all digital delay lock loops; bit rate 800 Mbit/s to 3.2 Gbit/s; burst mode memory interface; fast lock DLL; frequency 400 MHz to 1.6 GHz; jitter filtering ADDLL; power 6 mW; residual error; Clocks; Delays; Jitter; Noise; Random access memory; Synchronization;
Conference_Titel :
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5531-5
