A 35mW8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS

Author

Kull, Lukas ; Toifl, Thomas ; Schmatz, Martin ; Francese, Pier Andrea ; Menolfi, Christian ; Braendli, Matthias ; Kossel, Marcel ; Morf, Thomas ; Andersen, Toke Meyer ; Leblebici, Yusuf

Author_Institution

IBM Res. - Zurich, Rueschlikon, Switzerland

fYear

2013

fDate

12-14 June 2013

Abstract

An asynchronous 8× interleaved redundant SAR ADC achieving 8.8GS/s at 35mW and 1V supply is presented. The ADC features pass-gate selection clocking scheme for time-skew minimization and per-channel gain control based on low-power reference voltage buffers. The sub-ADC stacks the capacitive SAR DAC (CDAC) with the reference capacitor to reduce the area and enhance the settling speed. It achieves 38.5dB SNDR and 58fJ/conversion-step with a core chip area of 0.025mm² in 32nm CMOS SOI technology.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; silicon-on-insulator; CDAC; SAR ADC; SNDR; asynchronous interleaved redundant SAR ADC; bit rate 8.8 Gbit/s; capacitive SAR DAC; digital SOI CMOS; low-power capacitive reference buffers; low-power reference voltage buffers; pass-gate selection clocking scheme; per-channel gain control; power 35 mW; size 32 nm; time-skew minimization; voltage 1 V; CMOS integrated circuits; CMOS technology; Capacitance; Capacitors; Clocks; Layout; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2013 Symposium on

Conference_Location

Kyoto

Print_ISBN

978-1-4673-5531-5

Type

conf

Filename

6578686