DocumentCode
630023
Title
An 8.5mW 5GS/s 6b flash ADC with dynamic offset calibration in 32nm CMOS SOI
Author
Chen, Vanessa H.-C ; Pileggi, Larry
Author_Institution
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear
2013
fDate
12-14 June 2013
Abstract
This paper describes a 5GS/s 6bit flash ADC fabricated in a 32nm CMOS SOI. The randomness of process mismatch is exploited to compensate for dynamic offset errors of comparators that occur during high speed operation. Utilizing the proposed calibration, comparators are designed with near-minimum size transistors and built-in reference levels. The ADC achieves an SNDR of 30.9dB at Nyquist and consumes 8.5mW with an FoM of 59.4fJ/conv-step.
Keywords
CMOS integrated circuits; analogue-digital conversion; calibration; comparators (circuits); silicon-on-insulator; CMOS SOI; SNDR; a process mismatch; analogue-digital conversion; built-in reference levels; comparators; dynamic offset calibration; dynamic offset errors; flash ADC; high speed operation; near-minimum size transistors; power 8.5 mW; size 32 nm; CMOS integrated circuits; Calibration; Clocks; Heuristic algorithms; Semiconductor device measurement; Transistors; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location
Kyoto
Print_ISBN
978-1-4673-5531-5
Type
conf
Filename
6578688
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