A 1Gbps LTE-advanced turbo-decoder ASIC in 65nm CMOS

Author

Belfanti, Sandro ; Roth, Christian ; Gautschi, Michael ; Benkeser, Christian ; Qiuting Huang

Author_Institution

Integrated Syst. Lab., ETH Zurich, Zurich, Switzerland

fYear

2013

fDate

12-14 June 2013

Abstract

This paper presents a turbo-decoder ASIC for 3GPP LTE-Advanced supporting all specified code rates and block sizes. The highly parallelized architecture employs 16 SISO decoders with an optimized state-metric initialization scheme that reduces SISO-decoder latency, which is key for achieving very-high throughput. A novel CRC implementation for parallel turbo decoding prevents the decoder from performing redundant turbo iterations. The 65nm ASIC achieves a record data throughput of 1.013Gbps at 5.5 iterations with unprecedented energy efficiency of 0.17nJ/bit/iter.

Keywords

3G mobile communication; Long Term Evolution; decoding; 3GPP LTE advanced; CMOS; LTE advanced turbo decoder ASIC; SISO decoder latency; optimized state metric initialization scheme; parallel turbo decoding; redundant turbo iterations; size 65 nm; unprecedented energy efficiency; Application specific integrated circuits; Bit error rate; Decoding; Iterative decoding; Long Term Evolution; Throughput; ASIC implementation; CRC; LTE-Advanced; early termination; mobile communications; turbo decoder;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2013 Symposium on

Conference_Location

Kyoto

Print_ISBN

978-1-4673-5531-5

Type

conf

Filename

6578696