A 0.9 pJ/bit, 12.8 GByte/s WideIO memory interface in a 3D-IC NoC-based MPSoC

Author

Dutoit, Denis ; Bernard, Christian ; Cheramy, S. ; Clermidy, F. ; Thonnart, Yvain ; Vivet, Pascal ; Freund, Christian ; Guerin, Vincent ; Guilhot, S. ; Lecomte, S. ; Qualizza, Gianni ; Pruvost, Julien ; Dodo, Yves ; Hotelier, Nicolas ; Michailos, Jean

Author_Institution

CEA, Leti, Grenoble, France

fYear

2013

fDate

12-14 June 2013

Abstract

3D Integrated Circuit (3D-IC) opens architecture opportunities for improved SoC-to-memory interconnect bandwidth between dies. This paper presents the design of a two-tier 3D-IC composed of one NoC-based MPSoC and one multi-channel WideIO mobile SDRAM stacked in a face-to-back configuration. Measurements of the 3D-IC show that the targeted 12.8 GByte/s bandwidth is achieved in worst case conditions, while offering a 0.9 pJ/bit 3D I/O link power efficiency.

Keywords

integrated circuit interconnections; integrated memory circuits; logic design; multiprocessing systems; network-on-chip; three-dimensional integrated circuits; 3D I/O link power efficiency; 3D integrated circuit; 3D-IC NoC-based MPSoC; SoC-to-memory interconnect bandwidth; architecture opportunities; face-to-back configuration; multichannel WideIO mobile SDRAM; two-tier 3D-IC; wideIO memory interface; Bandwidth; Integrated circuit interconnections; Memory management; Mobile communication; Random access memory; System-on-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2013 Symposium on

Conference_Location

Kyoto

Print_ISBN

978-1-4673-5531-5

Type

conf

Filename

6578712