Title :
A 10-Bit 800-MHz 19-mW CMOS ADC
Author :
Chiang, Shiuh-Hua Wood ; Hyuk Sun ; Razavi, Behzad
Author_Institution :
Univ. of California, Los Angeles, Los Angeles, CA, USA
Abstract :
A pipelined ADC employs charge-steering op amps to relax the trade-offs among speed, noise, and power consumption. Applying full-rate nonlinearity and gain error calibration, a prototype realized in 65-nm CMOS technology achieves an SNDR of 52.2 dB at an input frequency of 399.2MHz and an FoM of 53 fJ/conversion-step.
Keywords :
CMOS integrated circuits; analogue-digital conversion; operational amplifiers; CMOS ADC; CMOS technology; charge-steering op amps; frequency 399.2 MHz; frequency 800 MHz; full-rate nonlinearity; gain error calibration; pipelined ADC; power 19 mW; power consumption; size 65 nm; word length 10 bit; CMOS integrated circuits; Calibration; Clocks; Linearity; Noise; Operational amplifiers; Very large scale integration;
Conference_Titel :
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5531-5
