DocumentCode
630091
Title
A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin
Author
Min-Cheng Chen ; Chang-Hsien Lin ; Yun-Fang Hou ; Yi-Ju Chen ; Chia-Yi Lin ; Fu-Kuo Hsueh ; Hsin-Liang Liu ; Cheng-Tsai Liu ; Bo-Wei Wang ; Hsiu-Chih Chen ; Chun-Chi Chen ; Shih-Hung Chen ; Chien-Ting Wu ; Tung-Yen Lai ; Mei-Yi Lee ; Bo-Wei Wu ; Cheng-San
Author_Institution
Nat. Nano Device Labs. (NDL), Taiwan
fYear
2013
fDate
12-14 June 2013
Abstract
For the first time, 10nm Si-based bulk FinFETs 6T SRAM (beta ratio = 2) with novel multiple fin heights technology is successfully demonstrated with 25% better static noise margin at 0.6 V than single fin-height baseline. Meanwhile, presented technology also provides advantage in SRAM cell size by 20% scaling down. It can furthermore offer potential of beyond 10nm Si-based CMOS computing circuit technology.
Keywords
CMOS integrated circuits; MOSFET circuits; SRAM chips; elemental semiconductors; silicon; CMOS computing circuit technology; FinFET; SRAM; Si; size 10 nm; static noise margin; voltage 0.6 V; FinFETs; Logic gates; Noise; SRAM cells; Silicon; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location
Kyoto
Print_ISBN
978-1-4673-5531-5
Type
conf
Filename
6578756
Link To Document