Testing of N-stage pipelined ADC using test input regeneration and sliding window techniques

Pipelined Analog-to-Digital Converters (PADCs) are one of the main building blocks in communication systems. It is of big interest to find a simple low cost test for the PADC. The purpose of this paper is to find a simple low cost DC test for an N-stage PADC without the need of complex additional circuitry. In order to reach this objective, a new testing technique called Test Input Regeneration (TIR) is proposed. The TIR technique selects the test inputs that can be applied to the first stage of the N-stage and can be regenerated at the input of other stages. Based on the TIR technique, the sliding window technique is introduced in order to test the whole N-stage (including the time alignment and Digital Error Correction (DEC) circuits) achieving a high catastrophic fault coverage. The test was verified using the Eldo simulator provided by Mentor Graphics Corp. on 90nm CMOS model provided from MOSIS.