Evaluation of SRAM based FPGA performance by simulating SEU through fault injection

Author

Ibrahim, M.M. ; Asami, K. ; Mengu Cho

Author_Institution

Integrated Syst. Eng. Dept., Kyushu Inst. of Technol., Kitakyushu, Japan

fYear

2013

fDate

12-14 June 2013

Firstpage

649

Lastpage

654

Abstract

This paper presents the technique and results of Single Event Upsets fault injection in the configuration bit-stream of SRAM-based FPGAs through partial reconfiguration of configuration frames. The Xilinx Virtex5 LX50 is used in the experiments. The Single Event Upset controller macro is used injecting faults to random locations of the FPGA bit-stream. The effects were studied on a design consisting of 4 embedded processor systems implemented in the FPGA. MATLAB is used for developing the external fault injection control environment.

Keywords

SRAM chips; embedded systems; fault diagnosis; field programmable gate arrays; integrated circuit design; radiation hardening (electronics); FPGA; MATLAB; SEU; SRAM; Xilinx Virtex5 LX50; embedded processor system; external fault injection control environment; partial reconfiguration frame; single event upset controller macro; Field programmable gate arrays; Orbits; Random access memory; Redundancy; Single event upsets; Space vehicles; Table lookup; Embedded Systems; FPGA; Fault Injection; Fault Tolerance; Single Event Upset;

fLanguage

English

Publisher

ieee

Conference_Titel

Recent Advances in Space Technologies (RAST), 2013 6th International Conference on

Conference_Location

Istanbul

Print_ISBN

978-1-4673-6395-2

Type

conf

DOI

10.1109/RAST.2013.6581290

Filename

6581290