DocumentCode
631370
Title
D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems
Author
Cancare, Fabio ; Pilato, Christian ; Cazzaniga, A. ; Sciuto, Donatella ; Santambrogio, Marco D.
Author_Institution
Politec. di Milano, Milan, Italy
fYear
2013
fDate
10-12 July 2013
Firstpage
1
Lastpage
6
Abstract
Dynamic self reconfigurable embedded systems are gathering, day after day, an increasing interest from both the scientific and the industrial world. At the same time, however, the need of a comprehensive and easy to use tool which can guide designers through the whole implementation process is becoming stronger. Up to now every proposed methodology for implementing dynamic self reconfigurable systems is architecture-centered. In most cases the system development process is time consuming and requires a very specific technical background. Aim of this work is to provide a fast brain to bit design flow whose goal is to simplify the dynamic reconfigurable system development process by shifting the designer focus from the architecture point of view to the application point of view: designers will not need to possess Dynamic Reconfigurability expertise but just to be skilled with the application domain.
Keywords
embedded systems; field programmable gate arrays; reconfigurable architectures; D-RECS; PDR; SDR; Simulink blocks; design flow; high level modeling phase; low level implementation phase; model-based design development environment; self dynamic reconfigurable FPGA-based system; time consumption; Computer architecture; Field programmable gate arrays; Hardware; Hardware design languages; Runtime; Software packages;
fLanguage
English
Publisher
ieee
Conference_Titel
Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013 8th International Workshop on
Conference_Location
Darmstadt
Print_ISBN
978-1-4673-6180-4
Type
conf
DOI
10.1109/ReCoSoC.2013.6581550
Filename
6581550
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