Low-power robust complementary polarizer STT-MRAM (CPSTT) for on-chip caches

Author

Xuanyao Fong ; Roy, Kaushik

Author_Institution

Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

fYear

2013

fDate

26-29 May 2013

Firstpage

88

Lastpage

91

Abstract

A spin-transfer torque MRAM with complementary polarizers, suitable for on-chip caches, is proposed in this paper. The average critical current for write in our proposed structure is lower than standard STT-MRAM, improving write-ability and reliability. Our proposed structure also has self-referencing differential read operation having subnanosecond read delay, and lower read disturb torque, improving sensing margin and disturb margin by 20%-60% and 55%-70% over standard STT-MRAM, respectively.

Keywords

cache storage; critical currents; integrated circuit reliability; low-power electronics; microprocessor chips; random-access storage; CPSTT; STT-MRAM; critical current; differential read operation; low-power robust complementary polarizer; magnetic random access memory; on-chip caches; reliability; spin-transfer torque; subnanosecond read delay; write-ability; Magnetic tunneling; Perpendicular magnetic anisotropy; Saturation magnetization; Sensors; System-on-chip; Torque; Complementary polarizers STT-MRAM; improved dual pillar STT-MRAM; spin-transfer torque MRAM (STT-MRAM); symmetric STT-MRAM write current; true self-reference differential STT-MRAM;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Workshop (IMW), 2013 5th IEEE International

Conference_Location

Monterey, CA

Print_ISBN

978-1-4673-6168-2

Type

conf

DOI

10.1109/IMW.2013.6582105

Filename

6582105