A 58nm gate length 512Mb B4-Flash memory - Verification of excellent scalability of B4-Flash memory -

Author

Shimizu, Shogo ; Shukuri, S. ; Ogura, Tsuneo ; Ajika, N. ; Arai, Hiroyuki ; Kobayashi, Kaoru ; Nakashima, Masahiro ; Iwamoto, Ken ; Morikawa, G. ; Tanaka, B. ; Toyonaga, Masahiko ; Takeda, H. ; Wada, Kazuyoshi ; Mifuji, M.

Author_Institution

GENUSION, Inc., Amagasaki, Japan

fYear

2013

fDate

26-29 May 2013

Firstpage

163

Lastpage

165

Abstract

This paper describes a 58nm gate length 512Mb B4-Flash (Back Bias assisted Band-to-Band tunneling induced Hot Electron injection Flash) memory, which is the smallest gate length NOR until now. 58nm gate length cells have been fabricated by 90nm process utilizing gate slimming technique. 58nm B4-Flash cells have been confirmed its sufficient performance compared to those of 90nm B4-Flash cells for NOR operation. B4-HE programming scheme, in which the voltage between drain and source sets to 1.8V, allows more aggressive gate length scaling than that for conventional CHE programming NOR, consequently gate length has been successfully scaled down to 58nm.

Keywords

NOR circuits; flash memories; tunnelling; B4 flash memory; B4-HE programming; CHE programming; NOR operation; gate length scaling; gate slimming; memory size 512 MByte; size 58 nm; size 90 nm; voltage 1.8 V; Flash memories; Logic gates; Nonvolatile memory; Programming; Reliability; Scalability; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Workshop (IMW), 2013 5th IEEE International

Conference_Location

Monterey, CA

Print_ISBN

978-1-4673-6168-2

Type

conf

DOI

10.1109/IMW.2013.6582124

Filename

6582124