Power management in multi-core processors using automatic dynamic pipeline stage unification

In the recent years, the rapid development of microprocessors has raise up the demand for high-performance and fast processing computing systems capable of performing multiple tasks. Multi-core processors are increasingly advocated as a viable solution to achieve high performance, but under the constraints associated with power bounds. Maintaining the power consumption of processors at an acceptable level is still a challenge. For instance, the size of transistors is set to go down to as small as 22nm. When this size starts to decrease and go below 30nm, the sub-threshold leakage will become an issue since the current technique of dynamic voltage frequency scaling (DVFS) used to conserve energy will become less useful. The reason for this is that the transistor size will decrease and the absolute maximum voltage at which it can be operated will also decrease, but the lower limit voltage will remain the same at 2.3V_th where V_th is threshold voltage. Thereby, there is a clear demand for alternatives for managing the energy consumption in chip multi-processors (CMPs). In this paper, a variable stage pipelining (VSP) or pipeline stage unification (PSU) is investigated as a potential successor to the DVFS technique. Theoretical results are provided, showing that our dynamic pipeline stage unification approach can be efficient in terms of power consumption, chosen as performance metric.