Low power CMOS sub-threshold circuits

Emerging new applications, such as wireless sensor nodes powered by energy harvesters, demand the change of the circuit design paradigm. Namely, for the past years, designers aimed at the minimum delay point in the energy-delay space, while the aforementioned applications require that the minimum energy point becomes the priority. One of the ways to achieve low energy consumption, while neglecting performance, is to operate the transistor in the sub-threshold (weak inversion) operation region. Since CMOS is the most widely accepted circuit design methodology, it would be the easiest and the most cost-effective to use it to design sub-threshold digital circuits. In this paper we provide an overview of sub-threshold CMOS digital logic circuits possibilities and limitations. We show that the same topology can be used, just as in strong inversion operation region. It is also shown that, comparing to the standard CMOS inverter, the speed and the temperature characteristic of the CMOS inverter with the dynamic threshold in the sub-threshold operation region is better.