DocumentCode
633057
Title
Parallelization and performance analysis of the Simulated Annealing algorithm for graph coloring problem
Author
Becirspahic, Lejla ; Dulovic, Adisa ; Nosovic, Novica
Author_Institution
Fac. of Electr. Eng., Univ. of Sarajevo, Sarajevo, Bosnia-Herzegovina
fYear
2013
fDate
20-24 May 2013
Firstpage
1306
Lastpage
1309
Abstract
Vertex coloring is a subset of the graph coloring problem. It is of great importance in many applications. Vertex coloring implies a coloring of the vertices of the graph with minimal number of colors (k), so that adjacent vertices have different color. The paper presents a hybrid implementation of Simulated Annealing algorithm for k-coloring of the vertices of the graph. The programming has been done with the use of CUDA toolkit. In order to find out how the speedup is achieved by parallelization, a sequential implementation for the problem has been used as a starting point. The results of CUDA based program and sequential implementation are analyzed. This hybrid implementation shows significant improvement and can be used as base for future work.
Keywords
graph colouring; parallel architectures; simulated annealing; CUDA based program; graph coloring problem; hybrid implementation; k-coloring; parallelization analysis; performance analysis; sequential implementation; simulated annealing algorithm; vertex coloring; Color; Graphics processing units; Instruction sets; Kernel; Markov processes; Simulated annealing; Temperature distribution; CUDA; graph coloring; parallelization; simulated annealing;
fLanguage
English
Publisher
ieee
Conference_Titel
Information & Communication Technology Electronics & Microelectronics (MIPRO), 2013 36th International Convention on
Conference_Location
Opatija
Print_ISBN
978-953-233-076-2
Type
conf
Filename
6596461
Link To Document