Design flow and techniques for fault-tolerant ASIC

The paper presents a design flow for fault-tolerant CMOS ASICs which are immune to the single event upsets (SEU), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits and SEL protection switches (SPS) make the base for design of the highly reliable ASIC. The SPS had been designed, characterised, and verified before it became a standard library cell. The proposed design flow requires the standard design automation tools and a few additional steps during logic synthesis and layout generation. An extra step is necessary to generate the redundant design net-list including voters. Other two extra steps (definition of the power domains and placement of the SPS) have to be performed in the layout phase. The concept has been verified on the example of a shift-register.