Optimization of inference engine in CMOS analog fuzzy logic controllers

Analog implementation of Fuzzy Logic Controllers(FLCs) is the most efficient method when speed, power, and area are critical. Inference engine usually takes a large part of die area when the FLC has a large number of rules. In this paper is presented a method to reduce size of the inference engine in analog implementations of FLCs. This is done by identifying deterministic cases in the inference engine of an FLC and using only the necessary number of inference blocks. A method to identify active rules at any instance is proposed along with the necessary circuitry. To demonstrate the proposed method, an FLC with two inputs, and twenty five rules is designed. The inference engine is designed both through the regular way and also using the proposed method. The resulting decision surfaces have an error of about 3% with respect to each other, which shows the efficiency and veracity of the method. All the simulations have been carried out using HSPICE with level 49 parameters (BSIM3v3) in standard 0.35um CMOS technology.