DocumentCode :
634106
Title :
Hardware implementation of interval type-2 fuzzy logic controller
Author :
Mesri, Alireza ; Khoei, Abdollah ; Hadidi, Khayrollah
Author_Institution :
Microelectron. Res. Lab., Urmia Univ., Urmia, Iran
fYear :
2013
fDate :
14-16 May 2013
Firstpage :
1
Lastpage :
6
Abstract :
In this paper design of a general-purpose Interval Type-2 Fuzzy Logic Controller (IT2 FLC) is presented. For the fuzzifier block, a new fully programmable IT2 membership function generator (MFG) circuit based on Type-1(T1) MFG is proposed that uses a new method for slope tuning. The proposed slope tuning method, leads to smaller active area and also significantly smaller total die area by reducing the numbers of required pins in comparison with previous methods. Type-reducer block is designed based on the Nie-Tan type-reduction method which reduces hardware complexity. Moreover, a modified version of multiplier is employed in the defuzzifier block which reduces the chip area and enhances the speed performance. Also, a new min circuit is presented to realize the inference block which is perfectly compatible with other blocks. Small area, low power consumption and especially suitable programming method, makes the proposed FLC suitable for general-purpose applications. The proposed FLC has two inputs with one output that can be implemented in 0.028 mm2 in 0.18 μm CMOS technology. The maximum delay of the proposed FLC is about 157 ns that corresponds to 6.37 MFLIPS (fuzzy logic inference per second). Power consumption of the proposed FLC is 4.64 mW.
Keywords :
CMOS logic circuits; circuit complexity; function generators; fuzzy control; fuzzy reasoning; multiplying circuits; programmable logic devices; CMOS technology; IT2 FLC; MFLIPS; Nie-Tan type-reduction method; Type-1 MFG circuit; Type-reducer block design; chip area reduces; defuzzifier block; fully programmable IT2 membership function generator circuit; fuzzifier block; fuzzy logic inference per second; general-purpose interval Type-2 fuzzy logic controller; hardware complexity; inference block; modified multiplier version; power consumption; programming method; size 0.18 mum; slope tuning method; speed performance; Engines; Frequency selective surfaces; Fuzzy logic; Generators; Hardware; Phase change materials; Simulation; Defuzzifier; IT2 Fuzzifier; IT2 Inference Engine; IT2 Output Processor; Type-Reducer;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Engineering (ICEE), 2013 21st Iranian Conference on
Conference_Location :
Mashhad
Type :
conf
DOI :
10.1109/IranianCEE.2013.6599656
Filename :
6599656
Link To Document :
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