Design of high-throughput QC-LDPC decoder for WiMAX standard

Author

Heidari, Tahere ; Jannesari, Abumoslem

Author_Institution

Tarbiat Modares Univ., Tehran, Iran

fYear

2013

fDate

14-16 May 2013

Firstpage

1

Lastpage

4

Abstract

In this paper, a high throughput low-density parity-check (LDPC) decoder for 802.16e standard is presented. With simultaneous rows and columns processing, which reduced the number of clock cycles per iteration, the throughput of the decoder is improved. The proposed decoder architecture was designed for 802.16e standard with rate of 1/2 and code length of 2304 with 7-encodings style. It is synthesized on 130 nm CMOS technology by Synopsys Design Compiler. The obtained result in the operating frequency of 100 MHz shows total power consumption of 242mW and the chip area of 6.9 mm².

Keywords

CMOS integrated circuits; WiMax; cyclic codes; decoding; integrated circuit design; iterative methods; parity check codes; radiofrequency integrated circuits; telecommunication standards; CMOS technology; IEEE 802.16e standard; WiMAX standard; clock cycle per iteration; frequency 100 MHz; high-throughput QC-LDPC decoder; low-density parity-check decoder; power 242 mW; power consumption; size 130 nm; synopsys design compiler; Clocks; Decoding; Hardware; IEEE 802.16 Standards; Parity check codes; Throughput; High Throughput; LDPC; Min Sum Algorithm; QC_LDPC; decoder;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering (ICEE), 2013 21st Iranian Conference on

Conference_Location

Mashhad

Type

conf

DOI

10.1109/IranianCEE.2013.6599692

Filename

6599692