Title :
A 32kb 90nm 10T-cell sub-threshold SRAM with improved read and write SNM
Author :
Hassanzadeh, S. ; Zamani, Mahdi ; Hajsadeghi, Khosrow
Author_Institution :
Dept. of Electr. Eng., Sharif Univ. of Technol., Tehran, Iran
Abstract :
The constraints of power saving have compelled SRAM designers to consider sub-threshold area as a viable choice. The biggest barrier of this progress is the stability of SRAM´s cells and the correct operations. In this paper a 10T cell structure has been proposed with 90% read and 50% write SNM improvement in comparison to the conventional 6T cell. The hold SNM value is about the 6T cell SRAM. Also using differential read method in the proposed structure causes high read performance and using simpler sense amplifier. The symmetric configuration of this structure helps the SRAM has simpler layout and lower transistor mismatch. Using 90nm TSMC CMOS, 32kb 10T cell SRAM in sub-threshold area is simulated that confirms the proposed structure performance.
Keywords :
CMOS memory circuits; SRAM chips; amplifiers; circuit stability; integrated circuit design; transistor circuits; SNM improvement; SRAM cell; SRAM design; TSMC CMOS; cell structure; differential read method; hold SNM value; power saving constraints; read SNM; read performance; sense amplifier; size 90 nm; stability; storage capacity 32 Kbit; subthreshold SRAM; subthreshold area; transistor mismatch; write SNM; CMOS integrated circuits; Circuit stability; Layout; SRAM cells; Stability analysis; Transistors;
Conference_Titel :
Electrical Engineering (ICEE), 2013 21st Iranian Conference on
Conference_Location :
Mashhad
DOI :
10.1109/IranianCEE.2013.6599737