DocumentCode
634393
Title
A 10-b 100-MSPS low power pipeline ADC for high energy physics experiments
Author
Donno, A. ; D´Amico, S. ; De Matteis, M. ; Baschirotto, A.
Author_Institution
Dept. of Innovation Eng., Univ. of Salento, Lecce, Italy
fYear
2013
fDate
24-27 June 2013
Firstpage
201
Lastpage
204
Abstract
A 10b 100-MS/s five-stage pipeline analog-to-digital converter (ADC) is implemented in 65nm digital CMOS process with power-reduction techniques for high energy physics experiments. It achieves 6.9dB signal-to-noise and distorsion ratio (SNDR). 8.5dB signal-to-noise ratio (SNR), 9.2 effective number of bits (ENOB) for a full-scale input sine at nyquist frequency. The ADC power consumption is 12.7mW from a 1.2V supply. It occupies 0.8mm2 die area.
Keywords
CMOS digital integrated circuits; analogue-digital conversion; ENOB; Nyquist frequency; SNDR; digital CMOS process; effective number of bits; five-stage pipeline analog-to-digital converter; high energy physics experiments; low power pipeline ADC; power 12.7 mW; power-reduction techniques; signal-to-noise and distorsion ratio; size 65 nm; voltage 1.2 V; CMOS integrated circuits; Capacitance; Linearity; Observatories; Pipelines; Power demand; Topology; Analog to digital converter (ADC); Pipeline;
fLanguage
English
Publisher
ieee
Conference_Titel
Ph.D. Research in Microelectronics and Electronics (PRIME), 2013 9th Conference on
Conference_Location
Villach
Print_ISBN
978-1-4673-4580-4
Type
conf
DOI
10.1109/PRIME.2013.6603152
Filename
6603152
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